Data processing system input-output arrangement

ABSTRACT

A store and forward message switching system in which an auxiliary processor is employed to communicate with data lines having various data rates and data formats, and with disc and tape bulk data storage units. The data lines are terminated on data line buffers which are serviced by cooperation of two control circuits in the auxiliary processor operating on an overlap basis. Data is transferred between a fast access memory and the bulk data storage units under control of sequencing circuits in the auxiliary processor, and the function of servicing data line buffers is performed contemporaneously with the function of transferring data between the fast access memory and the bulk data storage units.

United States Patent [72! inventors Thomas'l'. Butler Downers Grove; Kenneth P. Kretsch, Sr., Wheaten; Sylvester M. Neville, Naperville; George W. Smith, J r.. Naperville, all of, III. (2II Appl. No. 830,343 [22] Filed June 4, 1969 [45] Patented June 22, 1971 [73] Assignee Bell Telephone Laboratories, Incorporated Murray Hill, Berkeley Heights, NJ.

[54] DATA PROCESSING SYSTEM INPUT-OUTPUT ARRANGEMENT 20 Claims, l5 Drawing Figs.

[52] U.S.Cl. 340/1725 [51] lnt.Cl G06f3/00 [50] Field ofSearch 340M725; 235/157 56] References Cited UNITED STATES PATENTS 3,099,818 711963 Murray 340/1725 CENTRAL CONTROL I I I I !0l I MEM BUS I I cammosasw' Primary Examiner-Raulfe B, Zache AttorneysR. .l. Guenther and R. B. Ardis ABSTRACT: A store and forward message switching system in which an auxiliary processor is employed to communicate with data lines having various data rates and data formats, and with disc and tape bulk data storage units. The data lines are terminated on data line buffers which are serviced by cooperation of two control circuits in the auxiliary processor operating on an overlap basis. Data is transferred between a fast access memory and the bulk data storage units under control of sequencing circuits in the auxiliary processor, and the function of servicing data line buffers is perfonned contemporaneously with the function of transferring data between the fast access memory and the bulk data storage units.

'CIRE'F CILITES' I m- TYPE AE I BUS MEM no I BQFFER PROCESSOR 114 I I I TRANSFER LF ACCESS 115 I I I CONTROL comma. I I CCT I ccr I I II6\ 11 I I SCAN CHARACTER I CONTROL HANDLING I I ccr CCT I I I :13 H I DATA STORE FFER STORE I I CONTROL ACCESS I L CCT CONTROL CCT s Ql ATA STORE I BUFFER STORE I i 141 I I31 I II I I I IDISCI DISC, ITADEI TAPE I gIcom, ICONT; Icom mom I Lmh I A s B I A I I I 2 DISC oIsc TAPE, IIFILE T FILE FILEI FILE I I L PATENTEUJUNZZISYI 3.587.058

sum 010F 14 F161! .A i CENTRAL PRoCEssoR b LINE FACILITIES \It IQII LF TYPEA i BUS I CENTRAL CONTROL MEM BUS BUFFER PRoCEssoR 1/4 TRANSFER LF ACCEss 115 CoNTRoL I CONTROL CCT CCT l l16 1173 f sCAN CHARACTER I CoNTRoL HANDLING CCT CCT J DATA sToRE UFFER STORE CoNTRoL ACCESS i CCT CONTROL CCT IRTA sToRE {FUFFER sToRE i ,141 lal DISC DISC TAPE TAPE [MEN ---1 com com com com I A B A B l 2 5% $1? I INVENTORS M NEVILLE I DIS(EI DISC TAPE APE 6. WISH/TH JR.

FIL FILE FILE ILE a? A B A B d, flM a ATTORNEY PATENTE [1 JUN 2 2 IQYI SHEET 03 OF FIG. 3

COUNTER REGISTER 5OMS COUNTER COUNTER FIRST "1" RESET CCT REGISTER ii I FIRST "1" TRAZ DET

TO "*CGC 202 PATENTEU JUHZEGT'; 3 5 735 SHEET 10 0F 14 FIG. 10

NORMAL MoDE 1P HP READ CONTROL wDRD STATE 1NM INCREMENT NS COUNTER GATE BR TR JHPI 1HP SAMPLE TR, cLEAR F0 2NM wA|T=(SR-TMA'z) GATE ADDRESS KR (TMAZ) 1 (TMAZ) GATE KR BlTS11-19 FR BITS 1H9 READ LF (SCAN-D 0R SCAN-O) 3W ADJUST RI 8 TYPE F/F SAMPLE TR, cLEAR F0 GATE ADDRESS- KR SIGNAL SR(IR25) (TMAz lHPI (T"'M Az SR) LEE (TMAZ S 4NM WAIT: (MRI-SR6) IHPI 1HP PATENTEUJUNNIGI'I 3,587,058

SHEEI 11 0F 14 FIG. 1/

INTERMEDIATE PRIORITY MODE READ CONTROL WORD (MLIF) GATE CONTROL WORD- MC(MLIF) sTATE IIP WAIT: (SR) GATE ADDRESS KR(SR) RESET MLIF O,S HPI (I-S R) 1HP READ LF(SCAN I MODE) SET RI F/F 21F SAMPLE FR RESET MLIHFAZ) GATE ADDRESS KR *flLl w T READ LF (SCAN-D) RESET FR F0, sAMPI E FR 31P M L WA|T:(HPI-SR'FAZ) GATE NEW ADDRESS- KR REsET MLII(FAZ) (I -A7) lHPI (FAZ) 1HP READ DsM woRD (OUTPUT ACTIVITY) 4IP SET McLw(II\IDIcAT0R-BIT=I GATE OSM wDRD-TR 1R5? 1HP READ LF (SCAN O) GATE (LF ANSWER-TR)- FR lIIPI 1HP SAMPLE FR, RESET F0 GATE ADDREss KR elP L WAIT:(HPI-SR-FAZ) SET MLIHFAZ), INCREMENT MC CTR(FAZ) SET MLIF(FAZ-MCLW) 517 INM lHPI (FAZ-MCLW) (FAZ'MCLW) 1HP PATENIEUJUTQQGT 3,587,058

SHEET 12 0F 14 FIG. 12

HIGH PRIORITY MODE NS ML l a READ HP CONTROL WORD STATE 1HP INCREMENT NS COUNTER GATE CONTROL WORD TR SAMPLE TR, RESET F0 WAIT: (SR-TM" AZ) ADJUST RI F/F GATE ADDRESS-*KR (TMAZ-O) READ LF (SCAN-I OR SCAN-O) 3HP SAMPLE FR GATE ADDRESS-*KR F A ZO FAz-TA? FAz-TAz-o) (FAZ-TAZ-I) READ LF(SCAN-D) RESET FR FO, SAMPLE FR SAMPLE TR, RESET TR FO(FMAZ) 4HP SIGNAL SR WAIT:(SR-TMAZ) GATE ADDRESS+KR V |(FMAZ-TMAZ) l (FMAZ) (FMAZ'TMAZ) RESET FR FO, SAMPLE FR SAMPLE TR, RESET TR FO(FMAZ) 5HP SIGNAL SR WA|T (SR-TMAZ) GATE ADDRESS-*KR (FMAZ-TMADI (FMAZ-TMAZ) 7 7 FIG. [3

I M ..E.

WAIT:(S R) STATE 0 GATE LINE ADDRESS LR ADJUST CSIO F/F READ CLASS OF SERVICE WORD I GATE IR cR REsET em I I INPUT OUTPUT TYPE TYPE B A OR c 2 READ INPUT 10 READ TRANSMIT BUFFER WORD WORD I I I I TYPE TYPE cIIAR. CHAR. A OR B C COUNT cOUNT CHAR. CHAR. NOT F|R5T OUNT COUNT FIRST WORD =2 =0 OR I WORD I I 3 WRITE HOPPER READ EMPTY BLOCK H READ CHARACTER ADDREss LOCATION WORD OUTPUT BUFFER I I T TYPE TYPE EMPTY 4 WRITE HOPPER 6 READ LAsT WORD A ORB C DATA OF DATA BLOCK I I LAsT NOT WORD LAsT TYPE WORD T EMPTY BLOCK 12 READ BUFFER WORD LOcATION WORD 0 TYPE C I I WRITE CHARACTER 8 WRITE DATA BLOCK I3 OUTPUT BUFFER I I /62B TYPE TYPE B A Rc TY E c I 0 WRITE INPUT 14 WRITE TRANSMIT BUFFER WORD WORD PATENTEDJUNBQISZI 3,587,058

SHEET 1; HF 14 FIG. [4

sTATE O INcREMENT Q cOuNTER 1 OBTAIN CONTROL WORD FROM B's OBTAIN ADDRESS WORD FROM 85 2 SEND INsTRucTION TO US (REAOOATA REOI (WRITE) 3 OBTAIN OATA wORO 5 OBTAIN OATA FROM 08 FROM BS (DATA REOI IOATA REO-OOONT32I L (COUNT132) 4 SEND OATA TO BS 6 sENO OATA TO US (COUNT=32) (COUNT=32) FIG. [5

FIG 6 FIG FIG

DATA PROCESSING SYSTEM INPUT-OUTPUT ARRANGEMENT BACKGROUND OF TH E INVENTION In a store and forward message switching system messages are received from data lines, stored in the system in bulk data storage units (e.g., disc and tape), and subsequently transmitted to destinations identified by address information accompanying the messages. Since large amounts of data must be handled on a real time basis, and a variety of operations (e.g., preparation of message headings, code conversion, error control, etc.) must be performed, an efficient data processing system is essential. To increase system efficiency, data lines are frequently terminated on autonomously operating data line buffers. The buffers convert system input data from the serial form, in which the data is received from the data lines, into the parallel form, which is employed within the message switching system, convert system output data from the parallel to the serial form for transmission on the data lines, and generate line status and identification information. A data processor services the data line buffers on a regular basis by obtaining line status and identification information and system input data from the buffers and by supplying system output data to the buffers. Furthermore, the data processor assembles input data from each data line, transfers assembled input messages to bulk data storage units, obtains output messages from bulk data storage units, and prepares the output messages for transmission to specified destinations. The tasks of servicing the data line buffers and of transferring data to and from bulk storage units are routine tasks which may consume a great deal of processor real time.

Accordingly, it is an object of this invention to provide a data processor for a message switching system wherein communications with data line buffers and bulk data storage units consume a minimum of processor real time.

It is another object of this invention to provide a means for performing the functions of obtaining line status information and input data from data line bufiers and of processing input data and transmitting output data to data line buffers on an overlap basisv It is another object of this invention to provide an input-output processor for servicing data lines, and for transferring data to and from bulk storage units contemporaneously therewith.

SUMMARY OF THE INVENTION In accordance with this invention, a data processor comprises two control circuits which function cooperatively on an overlap basis to service data line buffers terminating data lines having various data rates and data formats. The first of the two control circuits generates and transmits address information to the data line buffers to obtain line status and identification information and input data therefrom; the second control circuit stores input data in a fast access memory and obtains output data from the fast access memory and transmits the output data to the data line buffers in accordance with line status and identification information obtained by the first control circuit. A priority circuit resolves conflicts between the two circuits by allocating access to a communication bus interconnecting the data line buffers and the data processor, on a priority basis. Cooperation between the two circuits is assured by means of flip-flops and registers which are accessible to both control circuits. The first control circuit stores line status and identification information and system input data in the flip-flops and registers; the second control circuit obtains this information therefrom. The first control circuit is prevented from disturbing the state of the flip-flops and registers until the information is removed therefrom by the second control circuit. Independently operating sequencing circuits transfer data blocks between the fast access memory and bulk data storage units such as disc and tape. An access control circuit is provided to allocate access to the fast access memory, to the several autonomously operating circuits of the data processor, in accordance with a predetermined priority plan.

In accordance with one feature of this invention, servicing of data line buffers in a data switching system is accomplished by the cooperation of two control circuits operating contemporaneously and on an overlap basis.

In accordance with another feature of this invention, a first control circuit obtains line status and identification information and system input data from data line buffers and a second control circuit processes input data and transmits output data to data line buffers.

In accordance with another feature of this invention, the function of servicing data line buffers is performed contemporaneously with communication with bulk data storage units.

BRIEF DESCRIPTION OF THE DRAWING FIG. I is an illustrative block diagram of a message switching system;

FIGS. 2 through 9, arranged as shown in FIG. I5, form a schematic representation of a buffer processor in accordance with this invention;

FIGS. I0 through 12 are flow diagrams showing schematically the operations of the scan control circuit of this invention;

FIG. 13 is a flow diagram showing schematically the operation of the character handling circuit of this invention;

FIG. 14 is a flow diagram showing the operation of a representative one of four autonomously operating circuit arrangements which comprise the data store control circuit of this invention; and

FIG. 15 is a key sheet showing the arrangement of FIGS. 2 through 9.

GENERAL DESCRIPTION The illustrative embodiment of our invention is a store and forward message switching system, as shown in FIG. 1, comprising a Central Processor 100, a Buffer Processor 110, Line Facilities I20 comprising three types of data line buffers (Type A, Type B, and Type C) on which data lines having various data rates and data formats are terminated, at fast access Buffer Store 130, and a Data Store 140 comprising bulk data storage units. The line Facilities I20, the Buffer Store I30, and the Data Store I40 are accessed by the Buffer Processor which has a plurality of independently operating control circuits dedicated to the performance of predetermined functions. One such control circuit is the Transfer Control Circuit III which is responsive to command signals from the Central Processor I00 to store information received from the Central Processor 100 in the Buffer Store I30 and to fetch data from the Buffer Store I30 and to transmit the fetched data to the Central Processor 100. The Scan Control Circuit I16 and the Character Handling Circuit 117 function cooperatively to transfer system input data and system output data between the Line Facilities 120 and the Buffer Store 130. The Data Store Control Circuit I13 transfers data between the Data Store 140 and the Buffer Store I30. Access to the Buffer Store by each of the control circuits (II I, 113, I16, 117) is allocated upon request, by the Buffer Store Access Control Circuit 112, in accordance with a predetermined priority plan. Similarly, the Line Facilities Access Control Circuit I15 allocates access to the Line Facilities I20 upon request from the Scan Control Circuit 116 and the Character Handling Circuit 117.

The data line buffers of the Line Facilities 120 are autonomously operating character assembly-disassembly units each terminating a plurality of data lines. These buffers assemble serial data streams received from the data lines into multibit input data characters, and disassemble multibit output data characters into serial data streams for transmission on the data lines. The data line buffers are interconnected with the Buffer Processor 110 by means of the Line Facilities Bus 121, on which the Buffer Processor 110 transmits address informa' tion and system output data, and from which it receives line status and identification information and input datav Each data line buffer has facilities for recognizing a predetermined address appearing on the Line Facilities Bus 121 and for responding to that address either by accepting output data from the bus or by transmitting line status and identification information and system input data on the bus.

Addresses for the data line buffers are generated by the Scan Control Circuit "6 and transmitted to the buffers with a frequency determined by hardware timing counters in the Scan Control Circuit 6 and control words stored in the Buffer Store 130. The Scan Control Circuit H6 is arranged to operate in one of three modes: the HIGH PRIORITY mode, the INTERMEDIATE PRIORITY mode, and the NORMAL mode. Only specified types of buffers (Type A, B, or C), selected on the basis of the data rates of the lines terminated thereon, are serviced in each mode. The frequency with which these modes are entered to service a particular type buffer is determined by hardware timing counters (i.e., a 1.25 millisecond timing counter and a 50 millisecond timing counter). The particular buffers to be serviced in each mode are specified by the control words. Data buffer addresses are generated in each mode, on the basis of the information con tained in the control words, and are transmitted on the Line Facilities Bus I21 to obtain line status and identification infor' mation and system input data from the specified buffers. System input data characters, received from the buffers in response to an address transmitted by the Scan Control Circuit 116, are processed by the Character Handling Circuit 117 which assembles the input data characters into multicharacter words arid stores them in the Buffer Store I30. When system output data is to be transmitted to a certain buffer, the Character Handling Circuit I17 obtains the output data from the Buffer Store I30 and transmits the output data, and address information identifying the buffer, on the Line Facilities Bus I2].

Communications between the scan Control Circuit H6 and the Character Handling Circuit 1" take place by means of service request, input-output, and buffer type (i.e., A, B, or C) flip-flops and data and address registers in the Scan Control Circuit 116. When line status information obtained from a data line buffer indicates that a particular line is ready for input service, the Scan Control Circuit ll6 obtains the input data from the data line buffer, stores the data in the data register, sets the input-output flip-flop, and adjusts the buffer type flip-flops. Additionally, the address of the buffer and a line number identifying the line from which the input data was received. are stored in the address register. Similarly, when line status information obtained from a data buffer indicates that a particular line is ready for output service, the Scan Control Circuit II6 places the appropriate buffer address and line number in the address register, adjusts the buffer type flipflops and resets the input-output flip-flop. Finally, the Scan Control Circuit I16 signals the Character Handling Circuit 117 by setting the service request flip-flop. The Scan Control Circuit I16 is then prevented from disturbing the state of the flip-flops and the address and data registers as long as the service request flip-flop remains in the set state. The Character Handling Circuit "7 responds to the state of the service request flip-flop by recording the information contained in the input-output flip-flop and the address and data registers, in flip-flops and registers of the Character Handling Circuit 7, and by resetting the service request flip-flop. After the service request flip-flop has been reset, the Scan Control Circuit I16 is free to insert new information in the address and data registers and to adjust the input-output and buffer-type flipllops. If more lines are found needing service, the service request flip flop is set once again. It remains in the set state until the previous task has been completed by the Character Handling Circuit II7 and the new information has been obtained from the registers and flip-flops. In this manner, the Scan Control Circuit II6 and the Character Handling Circuit 117 function cooperatively on an overlap basis, and each performs a predetermined part of the total function of servicing data line buffers.

The Data Store I40 comprises two disc controllers and two tape controllers, each having corresponding disc or tape files. The four controllers are interconnected with the Buffer Processor via the Data Store Bus 141. The Data Store Control Circuit 3 in the Buffer Processor 110 comprises four independently operating sequencing circuits each designed to control the transfer of data between the Buffer Store I30 and a predetermined one of the four controllers of the Data Store I40. An instruction queue, stored in the Buffer Store 130, is uniquely associated with each of the four sequencing circuits and contains: information defining tasks to be performed by the associated sequencing circuit; addresses of data word locations in the Buffer Store and disc or tape file data area identification. Each of the sequencing circuits operates autonomously to read its associated queue and to execute the tasks defined therein. When the task is to transfer data from the Buffer Store 130 to the associated disc or tape controller, the data area identification information is first transmitted to the associated controller. Thereafter the data words are obtained from the designated data word locations in the Buffer Store I30 by the sequencing circuit. Each such obtained data word is temporarily stored in a dedicated register in the Data Store Control Circuit II3 and is subsequently transmitted to the associated controller. Similarly, when the task is to transfer data from the associated controller to the Buffer Store 130, the data area identification information is first transmitted to the controller. Thereafter the data is obtained from the controller by the sequencing circuit, is tem' porarily stored in the dedicated register, and is subsequently stored in the Buffer Store 130. The Data Store Control Circuit 113 further comprises a priority and control circuit for allocating, to each of the four sequencing circuits, access to the Data Store Bus I41 interconnecting the Buffer Processor H0 and the controllers of the Data Store 140, in accordance with a defined priority plan.

DETAILED DESCRIPTION The various circuits of the Buffer Processor 110 are depicted in greater detail in FIGS. 2 through 9. The processor is a synchronously operating machine comprising a Clock Circuit 500 which generates a plurality ofclock pulses each having a duration of a predetermined portion of a basic 5.5 microsecond machine cycle. The clock pulses are each generated once during each machine cycle and are employed throughout the processor in the generation of control pulses.

The Buffer Store Access Control Circuit Ill and the Line Facilities Access Control Circuit "5 grant access to the Buffer Store Bus I31 and the Line Facilities Bus I21, respectively, in accordance with a predetermined priority plan. These circuits comprise priority and control circuits for selecting the circuit which must be granted access and for controlling the transmission of the addresses and the transmission and receipt of data. The Transfer Control Circuit III, the Data Store Control Circuit 3, the Scan Control Circuit I16, and the Character Handling Circuit 117 are each arranged to request access to the Buffer Store I30 from the Buffer Store Access Control Circuit I12 which grants access on a priority basis in the above order.

Having requested access, the requesting circuit halts all further operations until a signal is received from a Buffer Store Access Control Circuit [I2 indicating that access has been granted. In response to such signal, the circuit which has been granted access gates address information, which includes a read or write command, to the Bufier Store Control Bus 5I2. The address information is subsequently gated from the Buffer Store Control Bus to the Buffer Store I30 via AND gate 701 under control of the Priority and Control Circuit 710. As a general rule, data to be written into the Buffer Store I30 is gated to the BR Register 511 under control of the circuit which was granted access, and to the Buffer Store I30 via the Buffer Store Write Bus 702 under control of the Priority and Control Circuit 710. An exception to this rule is data from the Transfer Control Circuit 111. Such data is transmitted directly to the Buffer Store Write Bus 702 without going through the BR Register 511 Data read from the Buffer Store 130 is generally first gated into the BR Register 51 1, via AND gate 516, under control of the Priority and Control Circuit H0, and is subsequently obtained therefrom under control of the circuit to which access was granted. However, data read from the Buffer Store 130 intended for the Transfer Control Circuit 111 is received in the DR Register 535 without going through the BR Register 511. Under certain conditions, data intended for the Character Handling Circuit 117 is received in the WR Register 603 without going through the BR Register 51 I.

The Scan Control Circuit 116 and the Character Handling Circuit 117 are also arranged to request access to the Line Facilities 120 from the Line Facilities Access Control Circuit 115; the Character Handling Circuit 117 having the higher priority. The circuit to which access is granted gates address information to the Line Facilities Control Bus 411. The priority and Control Circuit 413 subsequently gates the address information to the Line Facilities Bus 121 via AND gate 414. When the Character Handling Circuit 117 is granted access, the data contained in the CR Register 602 is gated to the Line Facilities Bus 121 via AND gate 415 under control of the Pri ority and Control Circuit 413. When the scan control circuit is granted access, the information received in response to the transmitted address is gated into either the IR Register 402 or the FR Register 222, depending upon the type of information which is received,

LINE FACILITIES 120 The Line Facilities 120 comprise three types of data line buffers (Types A, B, and C) to accommodate lines having various data rates. Each Type A buffer unit is arranged to accommodate up to 5l2 data lines having data rates ranging from 60 to I50 words per minute, and each unit has storage space for six data characters per line as follows: one assembled data character, one data character in the state of being assembled, one data character in the state of being disassembled, and three data characters ready for disassembly. Each Type B buffer unit is arranged to accommodate up to 64 lines having data rates up to 2400 bits per second, and can store four data characters per line as follows: an input data character being assembled, a completed input character, an output character being disassembled, and an output character awaiting disassembly. Each Type C buffer unit is arranged to accommodate l6 interofi'ice data lines having a data rate of 2400 bits per second and having a 23-bit data word format. Each such unit has facility to store four data words per line as follows: an input data word being assembled, a completed input word, an output word being disassembled, and an output word ready for disassembly.

As mentioned earlier, each data line buffer has facilities for recognizing a predetermined address appearing on the Line Facilities Bus 121. Simultaneously with the address, the Buffer Processor 110 also transmits commands on the Line Facilities Bus I21 which define the action expected of the addressed buffer. There are four such commands, namely, SCAN-I, SCAN-O, SCAN-D, and DATA. An addressed buffer transmits: status and line identification information ofinput lines in response to the SCAN-I command, status and line identifica tion information of output lines in response to the SCAN-O command, and received system input data in response to the SCAN-D command. An addressed buffer accepts system output data transmitted, on the Line Facilities Bus 121 by the Buffer Processor 110, in response to the DATA command.

scan CONTROL CIRCUIT I16 SCAN As shown in FIGS. 2 through 4, the Scan Control Circuit 116 comprises a plurality of registers (e.g., 222, 311) and counters (e.g., 251, 252), a Sequencing Circuit 20] and a Combining Gate Circuit 202. The Scan Control Circuit 116 is arranged to operate in three distinct modes, the NORMAL mode, the INTERMEDIATE PRIORITY mode, and the HIGH PRIORITY mode, to service the data line buffers of the system at predetermined repetition rates. Operations in each mode are controlled by the Sequencing Circuit 20I which assumes various states for each mode as indicated in FIGS. 10 through l2. The Sequencing Circuit 20] remains in each labeled state (e.g, INM, 3HP, etc.) for one 5.5 microsecond machine cycle unless specific conditions require that a particular state be held for more than one cycle. Outputs from the Sequencing Circuit 201 are combined in the Combining Gate Circuit 202 with clock pulses generated by the Clock 500 and other signal information obtained from various flip-flops, registers, and counters to produce control pulses for governing the operations of the Scan Control Circuit I16, Operations in the IN- TERMEDIATE PRIORITY mode and the NORMAL mode are interrupted approximately once every L25 milliseconds, to cause a transfer to the HIGH PRIORITY mode In the last named mode the Type C buffers and those of the Type B buffers which terminate data lines having data rates greater than I50 bits per second are served. The l.25 millisecond periods are defined by the High Priority Counter 252, an 8-bit binary counter, which is incremented once every 5.5 microseconds by a clock pulse generated by the Clock 500. When the High Priority Counter 252 reaches the count of 228, the HPI flipflop 241 is set. This serves as an indication to the Sequencing Circuit 20! that the HIGH PRIORITY mode must be entered. Upon completion of the work which is to be performed in the HIGH PRIORITY mode, the Sequencing Circuit 201 transfers to the INTERMEDIATE PRIORITY mode or the NORMAL mode. The INTERMEDIATE PRIORITY mode is entered, to service Type B buffers which terminate data lines having data rates of less than 150 bits per second, if either the MLI flipflop 244 is set or if the MLIF flip-flop 242 is reset. The MLI flip-flop 244 is set from the Combining Gate Circuit 202 when the state of the 50MS Counter 356 indicates that 50 milliseconds have elapsed. Thus, the INTERMEDIATE PRIORI- TY mode is entered from the HIGH PRIORITY mode approximately once every 50 milliseconds. The 50MS Counter 356 is incremented approximately once every 5 milliseconds by a clock pulse generated by the Clock 500. The MLIF flip-flop 242 is reset when work is begun in the INTERMEDIATE PRI- ORITY mode and is set only after servicing has been completed to all buffers which require service in the INTER- MEDIATE PRIORITY mode during a particular 50 millisecond period. Thus, the MLIF flip-flop 242 remains reset if the sequencer transfers from the INTERMEDIATE PRIORI- TY mode to the HIGH PRIORITY mode, as the result of a 1.25 millisecond interrupt, before all work in the INTER- MEDIATE PRIORITY mode is completedv Under such condi tions, the sequencer returns to the INTERMEDIATE PRIORI- TY mode, to resume the work therein, after completion of all the work in the HIGH PRIORITY mode. If the MLI flip-flop 244 is not set and the MLIF flip-flop 242 is not reset after the work in the HIGH PRIORITY mode is finished, the sequencer transfers from the HIGH PRIORITY mode to the NORMAL mode. In the NORMAL mode the Type A data buffers are serviced. Thus, the Sequencing Circuit 201 services Type A buffers, in the NORMAL mode, when there is no work to be done in either the HIGH PRIORITY or the INTERMEDIATE PRI ORITY mode.

In each of the three above-mentioned modes the function of the Scan Circuit 116 is essentially the same, i.e., to obtain line status and identification information and system input data for processing by the Character Handling Circuit 117. The following discussion further describes the operational steps performed by the Scan Control Circuit 116 in each of the three modes. In each mode control words are obtained from the Buffer Store which are employed to generate data buffer addresses. The data buffer addresses are employed to provide input service and output service to the buffers defined by the control words. Input service being defined as the obtaining of input line status and system input data; output service being defined as obtaining output line status and the transmitting of system output data to the buffers. in the case of input service, the Scan Control Circuit 116 generates a buffer address, obtains or generates a line number, and obtains the system input data from the data buffer defined by the buffer address The line address, comprising the buffer address and the line number, is saved in selected registers and the input data is stored in the 1R Register 402. Additionally, the R1 flip-flop 404 is set and one of the type flip-flops (e.g., 431) is set so as to indicate to the Character Handling Circuit 117 the type of buffer from which the input data was received. Similarly, in the case of output service, the line address is saved, the R1 flip flop 404 is reset, :1 the type flip-flops are adjusted. The type flip-flops comprise: the SA flipTlop 431 which is set when Type A buffers are serviced, the SB flip-flop 432 which is set when Type B buffers are serviced, and the SC flip-flop 433 which is set when Type C buffers are serviced. The Scan Control Circuit 116 sets the SR 11ip-flop 403 when input data has been received and when the line address of a line requiring output service has been stored in the appropriate register. The SR flip-flop 403 is reset from the Character Handling Circuit [17 after the necessary information has been obtained from the various registers and flip-flops of the Scan Control Circuit 116 and processing has begun. So long as the SR flip-flop 403 is in the set state the Scan Control Circuit 116 is prevented from disturbing the saved address, the stored input data, and the states of the R1 flip-flop 404 and the type flipflops. How ever, the Scan Control Circuit 116 does not necessarily stop all operations. Generally, several steps will be performed in the generation of a next address while the SR flip-flop 403 is set; but the saved address is not disturbed. When no further steps can be performed without disturbing the saved information, the Scan Control Circuit 116 waits until the SR flip-flop 403 is reset. When this flip-flop is reset the sequencer proceeds with the additional steps required for the obtaining of new input data or the assembling of a new buffer address for output service.

In the NORMAL mode, the Sequencing Circuit 20] may sume four states, lNM through 4NM, as indicated in FIG. 10. Entry into the NORMAL mode is made in state lNM, from either the HIGH PRIORITY mode or the INTERMEDIATE PRIORITY mode, service Type A data buffers. Upon entry into this mode a control word is read from the Buffer Store 130 which contains information necessary for the generation of Type A data buffer addresses. There is an input control word indicating the Type A buffers to be serviced for input service, and an output control word which indicates the Type A buffers to be serviced for output service. On entry into the NORMAL mode, the input control word is obtained and input service is provided to all data bulTers specified thereby, Next, the output control word is obtained and output service is provided to all buffers specified by the output control word. Subsequent to completion of performance of output service, the input control word is again obtained and input service performed foliowed by the performance of output service. This sequence is repeated until it is interrupted and the Sequencing Circuit 201 transfers to the HlGH PRIORITY mode. This interrupt occurs approximately once every 1.25 milliseconds. The input and output control words are stored in fixed adjacent address locations in the Buffer Store 130. The entire fixed address, except for the least significant bit thereof, is generated by the Combining Gate Circuit 202 just prior to the reading of the control word. The least significant bit of the ad dress is obtained from the Normal Scan Counter 251, a single bit binary counter, which is incremented each time a control word is obtained. The input control word is obtained if the output of the Normal Scan Counter 25] is and the output control word is obtained if it is a l in state INM the address of one of the control words is transmitted t the Buffer Store 130. The corresponding control word is received 1the BR Register 511 and gated to the TR Register 311 via Scan Bus 205. The control word comprises a 16-bit word in which there exists a 1" for each buffer to be serviced. There is a direct correspondence between the relative bit position of a l within the control word and the address of the buffer to be serviced such that the number which defines the bit position is the address of the corresponding buffer. In state 2NM the TR Register 311 is examined by means of the First l Detector 312, to determine the bit posi tion of the rightmost 1 (referred to herein as the first 1). The binary number of the bit position of the first "l," which represents a buffer address, is gated to the First l Memory 313 and is stored therein. Subsequently, the first 1 in the TR Register 311 is reset under control of the First 1 Reset Cir cuit 314, in case there are no 1s in the TR Register 311, a signal indicating this condition is generated on Conductor TAZ. 1f the TR Register 311 is all 0s" when it is sampled, this condition is recorded in the First 1 Memory 313 and a signal is generated on Conductor TMAZ. The latter signal is necessary to distinguish between the case where the TR Register 31] contained all "0's" before a sampling and the case where a l existed in the register which was reset by the First 1 Reset Circuit 314 immediately after the sampling opera tron.

The address stored in the First l Memory 313, and command information generated by the Combining Gate Circuit 202, are gated to the KR Register 401 via the Scan Bus 205 in state ZNM. it was mentioned earlier that an addressed buffer transmits status information of output lines in response to the SCAN-0 command. Accordingly, the SCAN-0 command is generated in state ZNM if the output control word was obtained in state lNM. it is characteristic of Type A data buffers that line status and identification information and input data are transmitted simultaneously in response to SCAN-D command. Accordingly, the SCAN-D command is generated in state ZNM if the input control word was obtained in state 1NM.

Gating of the address and command information into the KR register 40! is state ZNM will not take place unless the SR flip-flop 403 is reset, indicating that the information in the KR Register 401 has been obtained therefrom by the Character Handling Circuit 117. if the SR flip-flop 403 is found to be in the set state, the Sequencing Circuit 201 waits in state ZNM until the SR flip-flop 403 is reset. At that time the new buffer address and command information is gated into KR Register 401, and the Sequencing Circuit 201 advances to state 3NM after completion of state 2NM. Gating new information into the KR Register 401, waiting in state 2NM, and advancing to state 3NM will not take place if the TR Register 311 contained all "Us" at the time of examination. The all "0s condition is indicated by a signal on Conductor TMAZ. when such a signal is present, the Sequencing Circuit 20] returns to state lNM to obtain the next control word from the Buffer Store 130 instead of proceeding to state 3NM.

in state 3NM the buffer address and command information are gated from the KR Register 401 to the Line Facilities Control Bus 411 under control of the Combining Gate Circuit 202 and transmitted to the Line Facilities under control of the Priority and Control Circuit 413. The data buffer address is also gated to the FR Register 222 for later use by the Character Handling Circuit 117. The response received from the addressed Type A buffer comprises: a status bit indicating that one ofthe lines connected to the addressed buffer is ready for service; a line number identifying the line which is ready for service; and, in case of input service, one assembled input character. The line number and, in case of input service, the input character are gated into the 1R Register 402 via symbolic AND gate 421. The Combining Gate Circuit 202 responds to the status bit by setting the SR flip flop 403 thereby indicating to the Character Handling Circuit 117 that information in the 1R Register 402 is ready for processing. The RI flip-flop 404 is adjusted in state 3NM in accordance with the Normal Scan Counter 251 to indicate to the Character Handling Circuit 117 whether the operation is an input or an output operation During state 3NM, after the contents of the KR REgister 401 have been gated to the Line Facilities 120, the TR register is again sampled to find the nest l in the control word. The position of the next "I is recorded in the First "I" Memory 313 and the newly found l" is reset. The contents of the First l Memory 313, which forms a new buffer address, is subsequently gated into the KR Register 40I along with command information. If no more "I'l" exist in the TR register at this last sampling, the Sequencing Circuit 20! returns to state INM to read the next control word from the Buffer Store I30. However. if the TR register contains one or more "l's, the SR flip-flop 403 is examined. If the latest buffer response indicated that no lines were ready for service, the SR Ilip'flop 403 will be in the reset state. When such is the case, the new buffer address contained in the KR Register dot is transmitted to the Line Facilities [20. Thereafter, the functions of state JNM are repeated until such time as either all I s" of the TR Register 3" have been reset, or a line which is ready for ser vice has been found. When such a line is found, the SR flip flop 403 is set and the Sequencing Circuit 10l advances to state dNM. Having entered state NM, the Sequencing Circuit I remains in that state until the SR flipflop 403 is reset by the Character Handling Circuit 7 at which time a return is made to state JNM where the above-described functions are again performed.

The Sequencing Circuit 201 will operate in the NORMAL made until such time as the HPI flip-flop 14l is set indicating that the HIGH PRIORITY mode must be entered. Since it cannot be priorly determined in which of the NM states the Sequencing Circuit 20] will be found when the HPI flip-flop 241 is set, the HPI flip-flop is sampled at the end of each machine cycle. Thus, the transfer to the HIGH PRIORITY mode (state IHP) may occur in any of the NM states and oc curs even though the Sequencing Circuit MI is waiting in an NM state. When the Sequencing Circuit 20] returns to the NORMAL mode at a later time, the INM state will be entered to service all the Type A buffers regardless of the number of buffers which had been serviced before the interrupt occurred.

The INTERMEDIATE PRIORITY mode is entered approximately once every 50 milliseconds from the HIGH PRIORI- TY mode to service Type B data line buffers having data rates of less than I50 bits per second. A control word associated with the INTERMEDIATE PRIORITY mode is stored in the Buffer Store 130 and comprises the address of the first buffer ofa series of buffers to be serviced in sequence. This address is read from the Buffer store 130 and is employed to provide input service and output service to the first buffer of the series of buffers. The address is stored in the MC Counter 355 where it is incremented by I after input service and output service to the first buffer have been completed. The incremented ad dress is then employed to provide input and output service to the second buffer of the series. Thus, a new address is generated each time after service to a buffer has been completed by incrementing the MC Counter 355, and a plurality of buffers are serviced in sequence in this manner. Associsted with each data buffer is an output status map which contains information specifying the active output lines terminated on the data buffer. The output status map further contains an indicator bit which is in the set state if the associated buffer is the last of the series of buffers to be serviced in the INTERMEDIATE PRIORITY mode. The Sequencing Circuit 20! transfers to the NORMAL mode after the last buffer, as identified from the output status map, has been serviced for both input and output service.

The various states through which the Sequencing Circuit 20l progresses in the INTERMEDIATE PRIORITY mode are indicated in FIG. ll. Entry into this mode is always made in state llP. Entry into state 11? may occur under three conditions.

1. From the HIGH PRIORITY mode when the previously mentioned MLI flipd'lop 244 is set, i.e., when a 50 millisecond period has elapsed since the last servicing of buffers in the IN- TERMEDIATE PRIORITY mode.

2. From the HIGH PRIORITY mode when the previously mentioned MLIF flip-flop 242 is reset, i.e., previously started work in the INTERMEDIATE PRIORITY mode was interrupted before it was completed.

3. From state 6|? after one or more, but not all, buffers have been serviced for both input service and output service.

When state IIP is entered from the HIGH PRIORITY mode as a result of the MLI flip-flop 244 being in the set state, the control word is read from the Buffer Store I30 and gated into the MC Counter 355. In state II? the control word, which comprises the address of the first buffer of a series of buffers to be serviced, is gated into the KR Register 40l along with command information for subsequent transmission on the Line Facilities Bus I21. Furthermore, the MLIF flip-flop is reset in state IIP to indicate that servicing of buffers in the IN- TERMEDIATE PRIORITY mode has been started but has not been completed. When state If? is entered from the HIGH PRIORITY mode as a result of the MLIF flip-flop 242 being in the reset state, the address found in the MC Counter 355 is gated into the KR Register 401 without obtaining a control word from the Bufler Store I30. Similarly, when state HP is entered from state 6IP, the address found in the MC Counter 355 is gated to the KR Register 401 and no control word is obtained from the Buffer Store 130. The MLII flip'llop 243, which serves as an input-output indicator in the INTER MEDIATE PRIORITY mode, is examined in state III to determine whether input or output service must be performed When state HP is entered from the HIGH PRIORITY Mode to resume interrupted work in the INTERMEDIATE PRIORITY mode (i.e., the MLIF flip-fl0p 242 is reset), the state of the MLII flip-flop 243 indicates whether input or output service was in progress when the interrupt occurred. If the interrupt occurred during input service, the input service is performed, followed by output service, for the buffer whose address is found in the MC Counter 355. If the interrupt occurred during output service, only output service is performed for that buffer.

From state II? the Sequencing Circuit 20] advances to state III if input service is to be performed and to state Ill if output service is to be performed. In state ZIP the address information contained in the KR Register 401, comprising a buffer address and the SCAN-l command, is transmitted to the Line Facilities I20. The response from the addressed buffer comprises a 16-bit input service request word which is entered in the FR Register 222. The input service request word con tains a l for each line from which an input data character has been assembled in the data buffer. There is a direct correspondence between the relative position of a bit of the ser vice request word and a line number such that the number defining the bit position of a l in the service request word is the same as the line number of the corresponding data line. The 16-bit service request word is examined in the FR Register 222 by means of the First l" Detector 223. The position of the first I, which corresponds to the line number of a line requesting service, is stored in the First l Memory 224. Subsequently, a complete line address comprising the buffer address stored in the MC Counter 355, the line number, and the SCAN-D command is entered into the KR Register 401. In case the input service request word stored in the FR Register 222 is all 0,s" indicating that the addressed buffer has no lines ready for input service, the Sequencing Circuit 20! advances from state 2IP to state 4" to perform the necessary output service; otherwise, it advances to state 31?. In state SIP the address information contained in the RR Register 401 is transmitted to the Line Facilities and the addressed butt'er returns the assembled input data character obtained from the line whose line number was contained in the address information. The data character obtained from the Line Facilities 120 is entered in the IR Register 402 for further processing by the Character Handling Circuit I17, and the SR flipflop 403 is set. In state 3|? the first l of FR Register 222, which was detected in state ZIP, is reset, and the FR Register 222 is again sampled to detect the next l The location of the next "I," 

1. A data processing system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; a data processor comprising first control means for generating and transmitting address signals to said buffer means to obtain said line status information and said input data from said buffer means, and second control means, responsive to signals generated by said first control means and operating contemporaneously with said first control means, for processing said input data, and for transmitting said output data to said buffer means in accordance with said line status information.
 2. A data processing system in accordance with claim 1 wherein said data processor further comprises access control means for controlling access to said buffer means and for selectively allocating such access to said first and said second control means in accordance with a defined priority plan.
 3. A data processing system in accordance with claim 1 wherein said first control means comprises means for generating a first control signal in accordance with said obtained line status information; and wherein said second control means comprises means responsive to said first control signal to commence said processing and transmitting of data and means for generating a second control signal upon the commencement of said processing and transmitting of data; said first control means comprising means responsive to said first control signal to halt said transmission of address signals to saiD buffer means and responsive to said second control signals to resume said transmission of address signals, said first control means generates and transmits address signals during periods of time in which said second control means independently processes said input data and transmits said output data.
 4. A data processing system in accordance with claim 3 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information, and said input data from said first register means to said second register means.
 5. A data processing system in accordance with claim 3 wherein: said line status information comprises line identification numbers; said first control means further comprises first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information, and said input data from said first register means to said second register means.
 6. A data processing system in accordance with claim 1 wherein: said plurality of data lines comprises lines (Type A) having a low data transmission rate and lines (Type C) having a relatively higher data transmission rate; certain of said buffer means are associated with said lines having said low data rate and are responsive to certain of said address signals, and others of said buffer means are associated with said lines having said relatively higher data rate and are responsive to others of said address signals; and said first control means comprises means for periodically interrupting the generation and transmission of said certain address signals and for initiating transmission of said other address signals.
 7. A data processing system in accordance with claim 1 wherein: said plurality of data lines comprises lines (Type A) having a first data rate, lines (Type B) having a second data rate, and lines (Type C) having a third data rate; said buffer means comprise first, second, and third buffer means uniquely associated with said lines having said first, second, and third data rates respectively, said first, second, and third buffer means being responsive to first, second, and third address signals respectively; and said first control means comprises: means for generating first and second timing signals, means for interrupting the generation and transmission of said first and said second address signals and for initiating the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of the transmission of a specified number of third address signals in an uninterrupted sequence, said means for interrupting being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.
 8. A data switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means responsive to said command signals for transferring data between said main processor and said first memory means, second circuit means for transferring data between said first memory means and said second memory means, third circuit means for transferring data between said buffer means and said first memory means, and access control means for controlling access to said first memory means and for selectively allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.
 9. A data switching system in accordance with claim 8 wherein said second circuit means comprises a plurality of transfer control means and a plurality of register means uniquely associated with said transfer control means, said plurality of transfer control means operating concurrently to control the transfer of data between said associated register means and said first memory means and between said associated register means and said second memory means, said third circuit means further comprising access control means for controlling access to said second memory means and for selectively allocating such access to each of said plurality of transfer control means in accordance with a defined priority plan.
 10. A data switching system in accordance with claim 8 wherein said third circuit means comprises first control means for generating and transmitting address signals to said buffer means to obtain said line status information and said input data from said buffer means, and second control means, responsive to signals generated by said first control means and operating concurrently with said first control means, for processing said input data, and for transmitting said output date to said buffer means in accordance with said line status information.
 11. A data switching system in accordance with claim 10 wherein said third circuit means further comprises access control means for controlling access to said buffer means and for selectively allocating such access to said first and said second control means in accordance with a defined priority plan.
 12. A data switching system in accordance with claim 10 wherein: said plurality of data lines comprises lines having a first data rate, lines having a second data rate, and lines having a third data rate; said buffer means comprises corresponding first, second, and third buffer means uniquely associated with said lines having said first, second, and third data rates, and responsive to first, second, and third address signals, respectively; and said first control means comprises: means for generating first and second timing signals, means to interrupt the generation and transmission of said first and said second address signals and to initiate the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of generation and transmission of a specified number of said third address signals in sequence, said means for interrupting being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.
 13. A data switching system in accordance with claim 10 wherein: said first control means comprises means for generating a first control signal in accordance with said line status information; said second control means comprises means responsive to said first control signal to commence said processing and transmitting of data, and means for generating a second control signal upon the commencement of said processing and transmitting of data; and said first control means further comprises means responsive to said first control signal to halt the transmission of said address signals, and responsive to said second control signal to resume the tranSmission of address signals, whereby said first control means generates and transmits address signals to said buffer means during periods of time in which said second control means processes said input data and transmits said output data.
 14. A data switching system in accordance with claim 13 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information and said system input data from said first register means to said second register means.
 15. A message switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means for transferring data between said main processor and said first memory means in response to said command signals, second circuit means comprising a plurality of transfer control means and a corresponding plurality of register means, said transfer control means operating contemporaneously to control the transfer of data between said corresponding register means and said first memory means and between said corresponding register means and said second memory means, and access control means for controlling access to said second memory means and allocating such access in accordance with a defined priority plan, third circuit means comprising first control means for generating and transmitting address signals to said buffer means to obtain line status information and said input data therefrom, second control means, responsive to signals generated by said first control means and operating contemporaneously with said first control means, for processing said input data and for transmitting said output data to said buffer means, and access control means for controlling access to said buffer means and for allocating such access to said first and said second control means in accordance with a defined priority plan, timing means for supplying a plurality of timing pulses to said first, second, and third circuit means, and access control means for controlling access to said first memory means and for allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.
 16. A message switching system in accordance with claim 15 wherein said first control means comprises means for generating a first control signal in accordance with said line status information; and wherein said second control means comprises means responsive to said first control signals to commence said processing and transmitting of data, and means for generating second control signals upon the commencement of said processing and transmitting of data; said first control means comprising means responsive to said first control signal to halt the transmission of address signals, and to said second control signals to resume transmission of address signals, said first control means generates and transmits address signals during periods of time in which said second control means processes said input data and transmits said output data.
 17. A message switching system in accordance with claim 16 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer addresses corresponding to said transmitted address signals, and said input data; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer addresses, and said system input data from said first to said second register means.
 18. A message switching system in accordance with claim 15 wherein: said plurality of data lines comprises lines (Type A) having a first data rate, lines (Type B) having a second data rate, and lines (Type C) having a third data rate; said buffer means comprises corresponding first, second, and third buffer means associated with said lines and responsive to first, second, and third address signals, respectively; said first control means comprises: means for generating first and second timing signals, and means for interrupting the generation and transmission of said first and said second address signals and for initiating the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of transmission of a specified number of said third address signals, said interrupting means being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.
 19. In combination: a plurality of data signal sources adapted to generate status signals representing the functional activity of said sources, memory means for storing a plurality of control words at predetermined address locations, register means for storing information representing the memory addresses defining said predetermined address locations, timing means for generating timed interrupt signals, scan control means responsive to said timed interrupt signals to obtain control words from memory locations defined by said memory addresses and to scan said sources in accordance with said obtained control words, to determine the functional activity of the sources defined by said control words, and means responsive to said timed interrupt signals for selectively altering the contents of said register means.
 20. In combination: a data processor, a plurality of data handling devices connectable to said data processor, each of said devices being adapted to transmit input data to said data processor and to receive output data from said data processor in response to stimulation signals, first control means in said data processor for generating and transmitting said stimulation signals and for receiving said input data, and second control means, responsive to signals from said first control means and operating contemporaneously with said first control means, for processing said input data and transmitting said stimulation signals and said output data. 